1. Field of the Invention
The present invention relates to a current mode logic circuit, a source follower circuit, and a flip flop circuit which use MOS transistors that are capable of operating at a high speed in a low voltage by controlling the voltage of a body region in each MOS transistor.
2. Description of the Related Art
Conventional Example 1.
FIG. 1 is a circuit diagram showing a conventional current mode logic circuit using MOS transistors. In FIG. 1, the reference characters N1 and N2 designate N conductivity type Metal Oxide Semiconductor (hereinafter referred to as NMOS) transistors, "R1" and "R2" denote resistors, "I" indicates a constant current source, "IN" designates an input terminal connected to the gate of the NMOS transistor N1, "OUT" denotes an output terminal connected to the drain of the NMOS transistor, "REF" indicates an input terminal through which a reference voltage is supplied, "d" designates a node, "B" designates a body terminal of both the NMOS transistors N1 and N2.
Next, a description will be given of the operation of the conventional current mode logic circuit shown in FIG. 1.
Each of the voltage value, the current value, and the resistor value used in the following explanation is an example. For example, the magnitude of the power source voltage is 2.0 V, the magnitude of the reference voltage or reference voltage potential is 1.2 V, the resistor value of each of the resistors R1 and R2 is 1 K.OMEGA., the current value provided from the current source I is 0.4 mA, the threshold voltage of each of the NMOS transistors N1 and N2 is 0.4 V. The square wave voltages of 1.0 V and 1.4 V are supplied as a voltage of a low level and a voltage of a high level to the input terminal IN, respectively.
Firstly, it will be explained to determine a method of the voltage of the node d according to the input voltage supplied to the input terminal IN. The voltage of the node d becomes a voltage obtained by subtracting the voltage at the input terminal IN or the reference voltage REF from the threshold voltage of the NMOS transistors N1 and N2. When the voltage of the low level is supplied to the input terminal IN, the voltage at the node d becomes 0.8 V that is obtained by subtracting the supplied voltage from the threshold voltage of the NMOS transistor. When the voltage of the high level is supplied to the input terminal IN, the voltage at the node d becomes 1.0 V that is also obtained by subtracting the supplied voltage from the threshold voltage of the NMOS transistor.
Next, the ON-OFF operation of the NMOS transistors N1 and N2 and the change of the voltage at the output terminal OUT will be explained.
When the voltage 1.0 V of the low level is supplied to the input terminal IN, the voltage difference between the gate and the source of the NMOS transistor N1 becomes 0.2 V. Because this voltage difference is lower than the threshold voltage 0.4 V of the NMOS transistor N1, the NMOS transistor becomes OFF. On the other hand, because the voltage difference between the gate and the source of the NMOS transistor N2 becomes 0.4 V, the NMOS transistor is OFF. Accordingly, the voltage at the output terminal OUT becomes 2.0 V that is the voltage value of the constant current source.
Next, when the voltage of 1.4 V as the high level is supplied to the input terminal IN, the NMOS transistor N1 becomes ON and the NMOS transistor N2 becomes OFF, because the voltage difference between the gate and the source of the NMOS transistor N1 becomes 0.4 V and the voltage difference between the gate and the source of the NMOS transistor N2 becomes 0.2 V. In this case, because the current of 0.4 mA flows through the resistor R1, the voltage of the output terminal OUT becomes 1.6 V.
The following results were obtained.
______________________________________ Voltage (V) Voltage (V) at input terminal IN at output terminal OUT ______________________________________ 1.0 2.0 1.4 1.6 ______________________________________
According to the relationship of the voltages at the input/output terminals, as described above, it can be understood that the conventional current mode logic circuit shown in FIG. 1 has the function of an inverter that is capable of inverting an input voltage supplied to the input terminal IN.
Conventional Example 2.
FIG. 2 is a circuit diagram showing a flip flop circuit having a source follower circuit. In FIG. 2, the reference characters R1 to R4 designate resistors, Q1 to Q16 denotes NMOS transistors, CS1 to CS6 indicate constant current sources, C designates a clock input terminal through which a clock signal is inputted, D designates a data signal input terminal, VB1 denotes a first reference voltage terminal through which an input data item is inputted, and VB2 indicates a second reference voltage terminal to which a reference voltage is supplied.
The conventional flip flop circuit shown in FIG. 2 comprises a master circuit having the NMOS transistors Q1 to Q8, the resistors R1 and R2, and the constant current sources CS1 to CS3, and a slave circuit having the NMOS transistors Q9 to Q16, the resistors R3 and R4, the constant current sources CS4 to CS6. The configuration of the master circuit has the same as that of the slave circuit.
Next, a description will be given of the operation of the conventional flip flop shown in FIG. 2.
In the following explanation, the threshold voltage having the logical amplitude of a signal to be inputted to the data input terminal D is provided to the first reference voltage terminal VB1. The threshold voltage having the logical amplitude of a signal to be inputted to the clock input terminal C is provided to the second reference voltage terminal VB2. The pair of the NMOS transistors Q1 and Q2 and a pair of the NMOS transistors Q9 and Q10 form data write circuits, respectively. The pair of the NMOS transistors Q4 and Q5 and a pair of the NMOS transistors Q12 and Q13 form data store circuits, respectively.
When the value of the clock signal supplied to the clock signal input terminal C is a high level (for example, the logical value "1"), the NMOS transistors Q3 and Q14 become ON and the data write circuit in the master circuit and the data store circuit in the slave circuit become ON. The NMOS transistors Q6 and Q11 become OFF and the data store circuit in the master circuit and the data write circuit in the slave circuit become OFF. In this situation, when the value of the data signal ID1 supplied to the NMOS transistor Q1 is the high level, the NMOS transistor Q1 becomes ON and the NMOS transistor Q2 becomes OFF and the current determined by the magnitude of the constant current source CS1 flows in the resistor R1 through the NMOS transistors Q1 and Q3. Accordingly, the NMOS transistor Q8 outputs the output of the low level. On the other hand, because the NMOS transistor Q2 is OFF, no current flows in the resistor R2 and the NMOS transistor Q7 outputs the signal of the high level. Thereby, the data writing operation is performed in the master circuit. In the slave circuit, because the data store circuit enters the ON state, the data signal ID0 that is previously stored is kept and output to the data signal output terminals through the NMOS transistors Q15 and Q16. Like the operation of the NMOS transistors Q7 and Q8, the NMOS transistors Q15 and Q16 output signals that are complementary data items to each other in level, respectively. In this situation, when the voltage level of the clock signal supplied to the clock signal input terminal C is changed from the high level to the low level, the NMOS transistors Q6 and Q11 become ON and both the data store circuit in the master circuit and the data write circuit in the slave circuit become ON. The NMOS transistors Q3 and Q14 become OFF. The data write circuit in the master circuit and the data store circuit in the slave circuit become OFF.
The gate terminals of the NMOS transistors Q4 and Q5 are connected to the source terminal of the NMOS transistors Q7 and Q8, respectively. The NMOS transistor Q4 becomes ON and the NMOS transistor Q5 becomes OFF according to the data signal ID1 that has been inputted when the level of the clock signal is the high level. Thereby, the NMOS transistors Q7 and Q8 are continuously outputting the same value, that is obtained in the high level of the clock signal, to the slave circuit. Since the data write circuit in the slave circuit is in the ON state, the NMOS transistor Q7 outputs the signal of the high level and the NMOS transistor Q8 outputs the signal of the low level. Thereby, the NMOS transistor Q9 becomes ON and the NMOS transistor Q10 becomes OFF. Accordingly, the current, whose magnitude has been set by the constant current source CS4, flows in the resistor R3 through the NMOS transistors Q9 and Q11. Thereby, the NMOS transistor Q16 outputs the signal of the low level. Because the NMOS transistor Q10 is in the OFF state, no current flows in the resistor R4 and the NMOS transistor Q15 outputs the signal of the high level. Thus, the data is updated in the slave circuit.
The conventional flip flop circuit shown in FIG. 2 operates in the same manner described above when the level of the input data item inputted to the data input terminal is the low level. In this case, the NMOS transistor Q16 outputs the signal of the high level and the NMOS transistor Q15 outputs the signal of the low level.
As described above in detail, in the conventional flip flop circuit shown in FIG. 2, the master circuit inputs data when the level of the clock signal is the high level and the slave circuit updates its stored data when the level of the clock signal is the low level.
FIG. 3 is a timing chart showing the operation of the conventional flip flop circuit shown in FIG. 2. As shown in the timing chart of FIG. 3, the conventional flip flop circuit shown in FIG. 2 inputs the input data signal (D), ID0, ID2, ID3, . . . through the input terminal D according to the clock signal provided to the clock signal input terminal C, and then outputs the output data signal (Q) ID0, ID1, ID2, ID3, . . . , and the output data signal (QB) /ID0, /ID1, /ID2, /ID3, . . . through the output data terminals Q and QB, respectively, after several clocks have been elapsed.
FIG. 4 is a circuit diagram showing the constant current source incorporated in the conventional flip flop shown in FIG. 2. In FIG. 4, the reference character Id designates a current, Vcs denotes a voltage supplied to the gate of a MOS transistor, and Vd indicates a voltage supplied to the drain of the MOS transistor.
FIG. 5 is a diagram showing the current-voltage characteristic of the constant current source shown in FIG. 4. As shown in FIG. 5, in general, a voltage in the saturated region is used as the drain voltage to be supplied to the drain of the MOS transistor in order to flow the current Id of a constant value even if the drain voltage Id is changed. In addition, the voltage Vcs2 shown in FIG. 5 has a higher voltage level than that of the voltage Cs1. In order to obtain a desired current value Id, the voltage Vcs is set to the voltage Vcs2 or Vcs1.
In the conventional current mode logic circuit as the conventional example 1 shown in FIG. 1, because the voltage difference Vsb between the source and the body terminal is increased when the body terminal B of the NMOS transistors N1 and N2 is connected to the ground source voltage GND, the threshold voltage of the NMOS transistor is increased based on a substrate bias effect. As has been described in the conventional example 1, the conventional current mode logic circuit using the NMOS transistors N1 and N2 requires to input the input signal wave whose amplitude is approximately equal to that of the threshold voltage of the NMOS transistor. Therefore there is a drawback that it is difficult to decrease the voltage of the power source.
Furthermore, in the conventional current mode logic circuit as the conventional example 1 shown in FIG. 1, the resistors R1 and R2 are formed so that the values of them can be changed. In this case, it is possible to perform the current mode logic circuit at a high speed when the value of the resistor R1 is increased under the NMOS transistor N1 is ON and when the value of the resistor R1 is decreased under the NMOS transistor N1 is OFF.
Moreover, the conventional flip flop circuit having the configuration as the conventional example 2 shown in FIG. 2 uses the constant current power circuit having the characteristic shown in FIG. 3. Accordingly, in the source follower circuit comprising the NMOS transistor Q7 and the constant current source CS2, the NMOS transistor Q8 and the constant current source CS3, the NMOS transistor Q15 and the constant current source CS5, and the NMOS transistor Q16 and the constant current source CS6, although it is possible to perform the operation at a high speed when the level of the output data is changed from the low level to the high level, there is a drawback that the operation speed is decreased or down when the level of the output data is changed from the high level to the low level.
This means that the NMOS transistors Q7, Q8, Q15, and Q16 having a higher driving ability operate when the level of the output is increased, namely, the current that is proportion to square of the gate voltage flows when the load capacity in each of the NMOS transistors Q7, Q8, Q15, and Q16 is large, and on the other hand, when the output of the flip flop circuit is decreased, a current having a constant current value flows from the constant current source CS2, CS3, CS5, and CS6.